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EPM7256AEFC256-5 参数 Datasheet PDF下载

EPM7256AEFC256-5图片预览
型号: EPM7256AEFC256-5
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 5.5ns, 256-Cell, CMOS, PBGA256, FINE LINE, BGA-256]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 64 页 / 437 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EPM7256AEFC256-5的Datasheet PDF文件第51页浏览型号EPM7256AEFC256-5的Datasheet PDF文件第52页浏览型号EPM7256AEFC256-5的Datasheet PDF文件第53页浏览型号EPM7256AEFC256-5的Datasheet PDF文件第54页浏览型号EPM7256AEFC256-5的Datasheet PDF文件第56页浏览型号EPM7256AEFC256-5的Datasheet PDF文件第57页浏览型号EPM7256AEFC256-5的Datasheet PDF文件第58页浏览型号EPM7256AEFC256-5的Datasheet PDF文件第59页  
MAX 7000A Programmable Logic Device Data Sheet  
The parameters in this equation are:  
MCTON  
=
Number of macrocells with the Turbo Bit option turned  
on, as reported in the MAX+PLUS II Report File (.rpt)  
Number of macrocells in the device  
Total number of macrocells in the design, as reported in  
the Report File  
MCDEV  
MCUSED  
=
=
fMAX  
togLC  
=
=
Highest clock frequency to the device  
Average percentage of logic cells toggling at each clock  
(typically 12.5%)  
A, B, C  
=
Constants, shown in Table 31  
Table 31. MAX 7000A ICC Equation Constants  
Device  
A
B
C
EPM7032AE  
EPM7064AE  
EPM7128A  
EPM7128AE  
EPM7256A  
EPM7256AE  
EPM7512AE  
0.71  
0.71  
0.71  
0.71  
0.71  
0.71  
0.71  
0.30  
0.30  
0.30  
0.30  
0.30  
0.30  
0.30  
0.014  
0.014  
0.014  
0.014  
0.014  
0.014  
0.014  
This calculation provides an ICC estimate based on typical conditions  
using a pattern of a 16-bit, loadable, enabled, up/down counter in each  
LAB with no output load. Actual ICC should be verified during operation  
because this measurement is sensitive to the actual pattern in the device  
and the environmental operating conditions.  
Altera Corporation  
55  
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