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EPM7192SQC160-10 参数 Datasheet PDF下载

EPM7192SQC160-10图片预览
型号: EPM7192SQC160-10
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 62 页 / 1087 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000 Programmable Logic Device Family Data Sheet  
Programmable Interconnect Array  
Logic is routed between LABs via the programmable interconnect array  
(PIA). This global bus is a programmable path that connects any signal  
source to any destination on the device. All MAX 7000 dedicated inputs,  
I/ O pins, and macrocell outputs feed the PIA, which makes the signals  
available throughout the entire device. Only the signals required by each  
LAB are actually routed from the PIA into the LAB. Figure 7 shows how  
the PIA signals are routed into the LAB. An EEPROM cell controls one  
input to a 2-input ANDgate, which selects a PIA signal to drive into the  
LAB.  
Figure 7. PIA Routing  
To LAB  
PIA Signals  
While the routing delays of channel-based routing schemes in masked or  
FPGAs are cumulative, variable, and path-dependent, the MAX 7000 PIA  
has a fixed delay. The PIA thus eliminates skew between signals and  
makes timing performance easy to predict.  
I/O Control Blocks  
The I/ O control block allows each I/ O pin to be individually configured  
for input, output, or bidirectional operation. All I/ O pins have a tri-state  
buffer that is individually controlled by one of the global output enable  
signals or directly connected to ground or VCC. Figure 8 shows the I/ O  
control block for the MAX 7000 family. The I/ O control block of EPM7032,  
EPM7064, and EPM7096 devices has two global output enable signals that  
are driven by two dedicated active-low output enable pins (OE1and OE2).  
The I/ O control block of MAX 7000E and MAX 7000S devices has six  
global output enable signals that are driven by the true or complement of  
two output enable signals, a subset of the I/ O pins, or a subset of the I/ O  
macrocells.  
14  
Altera Corporation  
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