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EPM7192SQC160-10N 参数 Datasheet PDF下载

EPM7192SQC160-10N图片预览
型号: EPM7192SQC160-10N
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 62 页 / 1087 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000 Programmable Logic Device Family Data Sheet  
The instruction register length of MAX 7000S devices is 10 bits. Tables 7  
and 8 show the boundary-scan register length and device IDCODE  
information for MAX 7000S devices.  
Table 7. MAX 7000S Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EPM7032S  
EPM7064S  
EPM7128S  
EPM7160S  
EPM7192S  
EPM7256S  
1 (1)  
1 (1)  
288  
312  
360  
480  
Note:  
(1) This device does not support JTAG boundary-scan testing. Selecting either the  
EXTEST or SAMPLE/ PRELOAD instruction will select the one-bit bypass register.  
Table 8. 32-Bit MAX 7000 Device IDCODE  
Note (1)  
Device  
IDCODE (32 Bits)  
Part Number (16 Bits) Manufacturer’s 1 (1 Bit)  
Version  
(4 Bits)  
Identity (11 Bits)  
(2)  
EPM7032S  
EPM7064S  
EPM7128S  
EPM7160S  
EPM7192S  
EPM7256S  
0000  
0000  
0000  
0000  
0000  
0000  
0111 0000 0011 0010 00001101110  
0111 0000 0110 0100 00001101110  
0111 0001 0010 1000 00001101110  
0111 0001 0110 0000 00001101110  
0111 0001 1001 0010 00001101110  
0111 0010 0101 0110 00001101110  
1
1
1
1
1
1
Notes:  
(1) The most significant bit (MSB) is on the left.  
(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.  
20  
Altera Corporation  
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