MAX 7000 Programmable Logic Device Family Data Sheet
Figure 9 shows the timing requirements for the JTAG signals.
Figure 9. MAX 7000 JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 12 shows the JTAG timing parameters and values for MAX 7000S
devices.
Table 12. JTAG Timing Parameters & Values for MAX 7000S Devices
Symbol
Parameter
Min Max Unit
tJCP
tJCH
tJCL
TCKclock period
TCKclock high time
TCKclock low time
100
50
50
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJPSU JTAG port setup time
tJPH JTAG port hold time
45
tJPCO JTAG port clock to output
25
25
25
tJPZX JTAG port high impedance to valid output
tJPXZ JTAG port valid output to high impedance
tJSSU Capture register setup time
20
45
tJSH
Capture register hold time
tJSCO Update register clock to output
25
25
25
tJSZX Update register high impedance to valid output
tJSXZ Update register valid output to high impedance
For more information, see Application Note 39 (IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices).
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Altera Corporation
ALTERA [ ALTERA CORPORATION ]
