MAX 7000 Programmable Logic Device Family Data Sheet
The programming times described in Tables 6 through 8 are associated
with the worst-case method using the enhanced ISP algorithm.
Table 6. MAX 7000S tPULSE & CycleTCK Values
Device
Programming
Stand-Alone Verification
tVPULSE (s) CycleVTCK
tPPULSE (s)
CyclePTCK
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
4.02
4.50
5.11
5.35
5.71
6.43
342,000
504,000
0.03
0.03
0.03
0.03
0.03
0.03
200,000
308,000
528,000
640,000
764,000
1,024,000
832,000
1,001,000
1,192,000
1,603,000
Tables 7 and 8 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 7. MAX 7000S In-System Programming Times for Different Test Clock Frequencies
Device
fTCK
500 kHz 200 kHz 100 kHz 50 kHz
Units
10 MHz 5 MHz
2 MHz
1 MHz
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
4.06
4.55
5.19
5.45
5.83
6.59
4.09
4.60
5.27
5.55
5.95
6.75
4.19
4.76
5.52
5.85
6.30
7.23
4.36
5.01
5.94
6.35
6.90
8.03
4.71
5.51
6.77
7.35
8.09
9.64
5.73
7.02
7.44
9.54
10.86
14.58
21.75
25.37
29.55
38.49
s
s
s
s
s
s
9.27
13.43
15.36
17.63
22.46
10.35
11.67
14.45
Table 8. MAX 7000S Stand-Alone Verification Times for Different Test Clock Frequencies
Device
fTCK
500 kHz 200 kHz 100 kHz 50 kHz
Units
10 MHz 5 MHz
2 MHz
1 MHz
EPM7032S
EPM7064S
EPM7128S
EPM7160S
EPM7192S
EPM7256S
0.05
0.06
0.08
0.09
0.11
0.13
0.07
0.09
0.14
0.16
0.18
0.24
0.13
0.18
0.29
0.35
0.41
0.54
0.23
0.34
0.56
0.67
0.79
1.06
0.43
0.64
1.09
1.31
1.56
2.08
1.03
1.57
2.67
3.23
3.85
5.15
2.03
3.11
5.31
6.43
7.67
10.27
4.03
6.19
s
s
s
s
s
s
10.59
12.83
15.31
20.51
Altera Corporation
19
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