MAX 7000 Programmable Logic Device Family Data Sheet
Figure 4 shows a MAX 7000E and MAX 7000S device macrocell.
Figure 4. MAX 7000E & MAX 7000S Device Macrocell
Global Global
Logic Array
Clear
Clocks
from
2
I/O pin
Parallel Logic
Expanders
(from other
macrocells)
Fast Input Programmable
Select Register
Register
Bypass
to I/O
Control
Block
PRN
D/T
Q
Clock/
Enable
Select
Product-
Term
Select
Matrix
ENA
CLRN
VCC
Clear
Select
to PIA
Shared Logic
Expanders
36 Signals
from PIA
16 Expander
Product Terms
Combinatorial logic is implemented in the logic array, which provides
five product terms per macrocell. The product-term select matrix allocates
these product terms for use as either primary logic inputs (to the ORand
XORgates) to implement combinatorial functions, or as secondary inputs
to the macrocell’s register clear, preset, clock, and clock enable control
functions. Two kinds of expander product terms (“expanders”) are
available to supplement macrocell logic resources:
■
■
Shareable expanders, which are inverted product terms that are fed
back into the logic array
Parallel expanders, which are product terms borrowed from adjacent
macrocells
The Altera development system automatically optimizes product-term
allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
Altera development software then selects the most efficient flipflop
operation for each registered function to optimize resource utilization.
10
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
