MAX 7000 Programmable Logic Device Family Data Sheet
The MAX 7000 architecture supports 100% TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. The
MAX 7000 architecture easily integrates multiple devices ranging from
PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 7000 devices
are available in a wide range of packages, including PLCC, PGA, PQFP,
RQFP, and TQFP packages. See Table 5.
Table 5. MAX 7000 Maximum User I/O Pins
Note (1)
Device
44-
Pin
44-
Pin
44-
Pin
68-
Pin
84- 100- 100-
160-
Pin
160- 192-
208-
Pin
208-
Pin
Pin
Pin
Pin
Pin
Pin
PLCC PQFP TQFP PLCC PLCC PQFP TQFP PQFP PGA
PGA
PQFP RQFP
EPM7032
36
36
36
36
36
36
36
36
36
EPM7032S
EPM7064
52
52
68
68
64
68
68
64
64
68
EPM7064S
EPM7096
68
76
84
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S
100
84 84 (2) 100
84
104
84 (2) 104
124
124
124
132 (2)
164
164
164 (2)
164
Notes:
(1) When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins
become JTAG pins.
(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see
the Operating Requirements for Altera Devices Data Sheet.
MAX 7000 devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000 architecture accommodates a
variety of independent combinatorial and sequential logic functions. The
devices can be reprogrammed for quick and efficient iterations during
design development and debug cycles, and can be programmed and
erased up to 100 times.
Altera Corporation
5
ALTERA [ ALTERA CORPORATION ]
