MAX 7000 Programmable Logic Device Family Data Sheet
Table 34. EPM7160S Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
t
Register clear time
PIA delay
2.4
1.6
3.0
2.0
3.0
1.0
4.0
2.0
ns
ns
ns
CLR
t
t
(7)
(8)
PIA
Low-power adder
11.0
10.0
11.0
13.0
LPA
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5) The f
(6) Operating conditions:
values represent the highest frequency for pipelined data.
MAX
V
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
Tables 35 and 36 show the EPM7192S AC operating conditions.
Table 35. EPM7192S External Timing Parameters (Part 1 of 2)
Symbol Parameter Conditions
Note (1)
Speed Grade
-10
Min Max Min Max Min Max
Unit
-7
-15
t
t
Input to non-registered output C1 = 35 pF
7.5
7.5
10.0
10.0
15.0
15.0
ns
ns
PD1
PD2
I/O input to non-registered
output
C1 = 35 pF
t
t
t
Global clock setup time
Global clock hold time
4.1
0.0
3.0
7.0
0.0
3.0
11.0
0.0
ns
ns
ns
SU
H
Global clock setup time of fast
input
3.0
FSU
t
Global clock hold time of fast
input
0.0
0.5
0.0
ns
FH
t
t
t
t
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
C1 = 35 pF
4.7
5.0
8.0
ns
ns
ns
ns
CO1
CH
3.0
3.0
1.0
4.0
4.0
2.0
5.0
5.0
4.0
CL
ASU
48
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
