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EPM240T100I5N 参数 Datasheet PDF下载

EPM240T100I5N图片预览
型号: EPM240T100I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 7.5ns, 192-Cell, CMOS, PQFP100, 16 X 16 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 88 页 / 838 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–6
Chapter 2: MAX II Architecture
Logic Elements
Figure 2–5.
LAB-Wide Control Signals
Dedicated
LAB Column
Clocks
Local
Interconnect
Local
Interconnect
4
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclk1
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk2
asyncload
or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the MAX II architecture, the LE, is compact and provides
advanced features with efficient logic utilization. Each LE contains a four-input LUT,
which is a function generator that can implement any function of four variables. In
addition, each LE contains a programmable register and carry chain with carry-select
capability. A single LE also supports dynamic single-bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of interconnects:
local, row, column, LUT chain, register chain, and DirectLink interconnects. See