MAX 3000A Programmable Logic Device Family Data Sheet
Figure 1. MAX 3000A Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
INPUT/GCLRn
6 or 10 Output Enables (1)
6 or 10 Output Enables (1)
LAB A
2 to
LAB B
2 to
36
36
16
I/O
Control
Block
Macrocells
1 to 16
Macrocells
17 to 32
16
I/O
Control
Block
2 to 16 I/O
2 to 16 I/O
16
16
6 or 10
2 to 16
2 to 16
6 or 10
LAB C
LAB D
PIA
2 to
16
2 to
16
36
36
I/O
Control
Block
Macrocells
33 to 48
Macrocells
49 to 64
I/O
Control
Block
2 to 16 I/O
2 to 16 I/O
16
16
6 or 10
6 or 10
2 to 16
2 to 16
Note:
(1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have
10 output enables.
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high–performance LABs. LABs consist of 16–macrocell arrays, as shown
in Figure 1. Multiple LABs are linked together via the PIA, a global bus
that is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■
■
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Altera Corporation
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