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EPM3064ATC100-4 参数 Datasheet PDF下载

EPM3064ATC100-4图片预览
型号: EPM3064ATC100-4
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件
文件页数/大小: 46 页 / 715 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 3000A Programmable Logic Device Family Data Sheet  
MAX 3000A devices can be programmed in–system via an industry–  
standard four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system  
programmability (ISP) offers quick, efficient iterations during design  
development and debugging cycles. The MAX 3000A architecture  
internally generates the high programming voltages required to program  
its EEPROM cells, allowing in–system programming with only a single  
3.3–V power supply. During in–system programming, the I/O pins are  
tri–stated and weakly pulled–up to eliminate board conflicts. The pull–up  
value is nominally 50 kΩ.  
In–System  
Programma-  
bility  
MAX 3000A devices have an enhanced ISP algorithm for faster  
programming. These devices also offer an ISP_Donebit that ensures safe  
operation when in–system programming is interrupted. This ISP_Done  
bit, which is the last bit programmed, prevents all I/O pins from driving  
until the bit is programmed.  
ISP simplifies the manufacturing flow by allowing devices to be mounted  
on a printed circuit board (PCB) with standard pick–and–place equipment  
before they are programmed. MAX 3000A devices can be programmed by  
downloading the information via in–circuit testers, embedded processors,  
the MasterBlaster communications cable, the ByteBlasterMV parallel port  
download cable, and the BitBlaster serial download cable. Programming  
the devices after they are placed on the board eliminates lead damage on  
high–pin–count packages (e.g., QFP packages) due to device handling.  
MAX 3000A devices can be reprogrammed after a system has already  
shipped to the field. For example, product upgrades can be performed in  
the field via software or modem.  
The Jam STAPL programming and test language can be used to program  
MAX 3000A devices with in–circuit testers, PCs, or embedded processors.  
For more information on using the Jam STAPL programming and test  
language, see Application Note 88 (Using the Jam Language for ISP & ICR via  
an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP &  
ICR via an Embedded Processor) and AN 111 (Embedded Programming Using  
the 8051 and Jam Byte-Code).  
f
The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std.  
1532 specification. The IEEE Std. 1532 is a standard developed to allow  
concurrent ISP between multiple PLD vendors.  
Altera Corporation  
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