Chapter 9: Using User Flash Memory in MAX II Devices
9–25
Software Support for UFM Block
Table 9–9. SPI Interface Signals
Pin Description
SI Serial Data Input
Function
Receive data serially.
Transmit data serially.
SO
Serial Data Output
Serial Data Clock
SCK
The clock signal produced from the master device to
synchronize the data transfer.
nCS
Chip Select
Active low signal that enables the slave device to
receive or transfer data from the master device.
Data transmitted to the SIport of the slave device is sampled by the slave device at
the positive SCKclock. Data transmits from the slave device through SOat the
negative SCK clock edge. When nCSis asserted, it means the current device is being
selected by the master device from the other end of the SPI bus for service. When nCS
is not asserted, the SIand SCKports should be blocked from receiving signals from
the master device, and SOshould be in High Impedance state to avoid causing
contention on the shared SPI bus. All instructions, addresses, and data are transferred
with the MSB first and start with high-to-low nCStransition. The circuit diagram is
shown in Figure 9–25.
Figure 9–25. Circuit Diagram for SPI Interface Read or Write Operations
SI SO SCK nCS
Op-Code Decoder
Read, Write, and Erase
State Machine
SPI Interface
Control Logic
UFM Block
Address and Data Hub
Eight-Bit Status Shift Register
Opcodes
The 8-bit instruction opcode is shown in Table 9–10. After nCSis pulled low, the
indicated opcode must be provided. Otherwise, the interface assumes that the master
device has internal logic errors and ignores the rest of the incoming signals. Once nCS
is pulled back to high, the interface is back to normal. nCSshould be pulled low again
for a new service request.
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
