Chapter 9: Using User Flash Memory in MAX II Devices
9–15
Software Support for UFM Block
START and STOP Condition
The master always generates start (S) and stop (P) conditions. After the start
condition, the bus is considered busy. Only a stop (P) condition frees the bus. The bus
stays busy if the repeated start (Sr) condition is executed instead of a stop condition.
In this occurrence, the start (S) and repeated start (Sr) conditions are functionally
identical.
A high-to-low transition on the SDA line while the SCL is high indicates a start
condition. A low-to-high transition on the SDA line while the SCL is high indicates a
stop condition. Figure 9–12 shows the start and stop conditions.
Figure 9–12. Start and Stop Conditions
SDA
SCL
SDA
SCL
P
S
Stop Condition
Start Condition
Acknowledge
2
Acknowledged data transfer is a requirement of I C. The master must generate a clock
pulse to signify the acknowledge bit. The transmitter releases the SDA line (high)
during the acknowledge clock pulse.
The receiver (slave) must pull the SDA line low during the acknowledge clock pulse
so that SDA remains a stable low during the clock high period, indicating positive
acknowledgement from the receiver. If the receiver pulls the SDA line high during the
acknowledge clock pulse, the receiver sends a not-acknowledge condition indicating
that it is unable to process the last byte of data. If the receiver is busy (for example,
executing an internally-timed erase or write operation), it will not acknowledge any
2
new data transfer. Figure 9–13 shows the acknowledge condition on the I C bus.
Figure 9–13. Acknowledge on the I2C Bus
Data Output
By Transmitter
Not Acknowledge
Acknowledge
Data Output
By Receiver
SCL From
Master
S
Clock Pulse For
Acknowledgement
Start Condition
© October 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
