Chapter 5: DC and Switching Characteristics
5–15
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 2)
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Symbol
tOE
Parameter
Min Max Min Max Min Max Min Max Min Max Unit
Delay from data register clock to
data register output
180
—
180
—
180
—
180
—
180
—
ns
tRA
Maximum read access time
—
65
—
—
65
—
—
65
—
—
65
—
—
65
—
ns
ns
tOSCS
Maximum delay between the
OSC_ENArising edge to the
erase/program signal rising edge
250
250
250
250
250
tOSCH
Minimum delay allowed from the
erase/program signal going low to
OSC_ENAsignal going low
250
—
250
—
250
—
250
—
250
—
ns
© Novermber 2008 Altera Corporation
MAX II Device Handbook
ALTERA [ ALTERA CORPORATION ]
