5–14
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–20. tXZ IOE Microparameter Adders for Slow Slew Rate
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Standard
3.3-V LVTTL
Min Max Min Max Min Max Min Max Min Max Min Max Unit
16 mA
8 mA
—
—
—
—
—
—
—
206
891
206
891
222
943
161
—
—
—
—
—
—
—
–20
665
–20
665
–4
—
—
—
—
—
—
—
–247
438
—
—
—
—
—
—
—
1,433
1,332
1,433
1,332
213
—
—
—
—
—
—
—
1,446
1,345
1,446
1,345
208
—
—
—
—
—
—
—
1,454 ps
1,348 ps
1,454 ps
1,348 ps
3.3-V LVCMOS
8 mA
–247
438
4 mA
2.5-V LVTTL /
LVCMOS
14 mA
7 mA
–231
490
213
166
ps
ps
ps
717
210
166
161
3.3-V PCI
20 mA
258
1,332
1,345
1,348
1
The default slew rate setting for MAX II devices in the Quartus II design software is
“fast”.
Table 5–21. UFM Block Internal Timing Microparameters (Part 1 of 3)
MAX II / MAX IIG
MAX IIZ
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Symbol
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Unit
tACLK
Address register clock 100
period
—
100
—
100
—
100
—
100
—
100
—
ns
tASU
Address register shift
signal setup to
address register clock
20
20
20
20
—
20
—
20
—
20
—
20
—
20
—
ns
tAH
Address register shift
signal hold to address
register clock
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
ns
ns
ns
tADS
Address register data
in setup to address
register clock
tADH
Address register data
in hold from address
register clock
tDCLK
tDSS
Data register clock
period
100
60
—
—
100
60
—
—
100
60
—
—
100
60
—
—
100
60
—
—
100
60
—
—
ns
ns
Data register shift
signal setup to data
register clock
tDSH
Data register shift
signal hold from data
register clock
20
—
20
—
20
—
20
—
20
—
20
—
ns
MAX II Device Handbook
© August 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
