1–2
Chapter 1: Introduction
Features
Table 1–1 shows the MAX II family features.
Table 1–1. MAX II Family Features
EPM240
EPM570
EPM1270
EPM2210
Feature
LEs
EPM240G
EPM570G
EPM1270G
EPM2210G
EPM240Z
EPM570Z
570
240
192
570
440
1,270
980
2,210
1,700
240
192
Typical Equivalent Macrocells
Equivalent Macrocell Range
UFM Size (bits)
440
128 to 240 240 to 570 570 to 1,270 1,270 to 2,210
128 to 240
8,192
80
240 to 570
8,192
160
8,192
80
8,192
160
5.4
8,192
212
6.2
8,192
272
7.0
Maximum User I/O pins
t
PD1 (ns) (1)
fCNT (MHz) (2)
SU (ns)
4.7
7.5
9.0
304
1.7
304
1.2
304
1.2
304
1.2
152
152
t
2.3
2.2
tCO (ns)
4.3
4.5
4.6
4.6
6.5
6.7
Notes to Table 1–1:
(1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic
implemented in a single LUT and LAB that is adjacent to the output pin.
(2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number.
f
For more information about equivalent macrocells, refer to the MAX II Logic Element to
Macrocell Conversion Methodology white paper.
MAX II and MAX IIG devices are available in three speed grades: –3, –4, and –5, with
–3 being the fastest. Similarly, MAX IIZ devices are available in two speed grades: –6,
–7, with –6 being faster. These speed grades represent the overall relative
performance, not any specific timing parameter. For propagation delay timing
numbers within each speed grade and density, refer to the DC and Switching
Characteristics chapter in the MAX II Device Handbook.
Table 1–2 shows MAX II device speed-grade offerings.
Table 1–2. MAX II Speed Grades
Speed Grade
Device
EPM240
–3
–4
–5
–6
–7
v
v
v
—
—
EPM240G
EPM570
v
v
v
v
v
v
v
v
v
—
—
—
—
—
—
EPM570G
EPM1270
EPM1270G
EPM2210
EPM2210G
EPM240Z
EPM570Z
—
—
—
—
—
—
v
v
v
v
MAX II Device Handbook
© October 2008 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
