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EPM1270GF100C 参数 Datasheet PDF下载

EPM1270GF100C图片预览
型号: EPM1270GF100C
PDF下载: 下载PDF文件 查看货源
内容描述: MAX II器件系列 [MAX II Device Family]
分类和应用:
文件页数/大小: 86 页 / 1216 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–14  
Chapter 2: MAX II Architecture  
MultiTrack Interconnect  
functions from LE 1 to LE 10 in the same LAB. The register chain connection allows  
the register output of one LE to connect directly to the register input of the next LE in  
the LAB for fast shift registers. The Quartus II Compiler automatically takes  
advantage of these resources to improve utilization and performance. Figure 2–11  
shows the LUT chain and register chain interconnects.  
Figure 2–11. LUT Chain and Register Chain Interconnects  
Local Interconnect  
Routing Among LEs  
in the LAB  
LE0  
LUT Chain  
Routing to  
Adjacent LE  
Register Chain  
Routing to Adjacent  
LE's Register Input  
LE1  
LE2  
LE3  
LE4  
LE5  
LE6  
LE7  
LE8  
Local  
Interconnect  
LE9  
The C4 interconnects span four LABs up or down from a source LAB. Every LAB has  
its own set of C4 interconnects to drive either up or down. Figure 2–12 shows the C4  
interconnect connections from an LAB in a column. The C4 interconnects can drive  
and be driven by column and row IOEs. For LAB interconnection, a primary LAB or  
its vertical LAB neighbor can drive a given C4 interconnect. C4 interconnects can  
drive each other to extend their range as well as drive row interconnects for column-  
to-column connections.  
MAX II Device Handbook  
© October 2008 Altera Corporation