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EPM1270GF256A4N 参数 Datasheet PDF下载

EPM1270GF256A4N图片预览
型号: EPM1270GF256A4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Functional Description
Figure 2–1. MAX II Device Block Diagram
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Logic
Element
Logic
Element
Logic
Element
IOE
Logic
Element
Logic
Element
Logic
Element
Logic Array
BLock (LAB)
MultiTrack
Interconnect
IOE
Logic
Element
Logic
Element
Logic
Element
IOE
Logic
Element
Logic
Element
Logic
Element
MultiTrack
Interconnect
Each MAX II device contains a flash memory block within its floorplan.
On the EPM240 device, this block is located on the left side of the device.
On the EPM570, EPM1270, and EPM2210 devices, the flash memory block
is located on the bottom-left area of the device. The majority of this flash
memory storage is partitioned as the dedicated configuration flash
memory (CFM) block. The CFM block provides the non-volatile storage
for all of the SRAM configuration information. The CFM automatically
downloads and configures the logic and I/O at power-up, providing
instant-on operation.
f
For more information about configuration upon power-up, refer to the
Hot Socketing and Power-On Reset in MAX II Devices
chapter in the
MAX II
Device Handbook.
A portion of the flash memory within the MAX II device is partitioned
into a small block for user data. This user flash memory (UFM) block
provides 8,192 bits of general-purpose user storage. The UFM provides
writing. There are three LAB rows adjacent to this block, with column
numbers varying by device.
2–2Core
Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
March 2008