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EPM1270F256I4N 参数 Datasheet PDF下载

EPM1270F256I4N图片预览
型号: EPM1270F256I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 8.1ns, 980-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256]
分类和应用: LTE输入元件可编程逻辑
文件页数/大小: 108 页 / 1342 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX II Architecture
Logic Array
Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, a look-up table (LUT) chain, and register chain connection
lines. There are 26 possible unique inputs into an LAB, with an additional
10 local feedback input lines fed by LE outputs in the same LAB. The local
interconnect transfers signals between LEs in the same LAB. LUT chain
connections transfer the output of one LE’s LUT to the adjacent LE for fast
sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s
register within an LAB. The Quartus
®
II software places associated logic
within an LAB or adjacent LABs, allowing the use of local, LUT chain,
and register chain connections for performance and area efficiency.
Figure 2–3
shows the MAX II LAB.
Figure 2–3. MAX II LAB Structure
Row Interconnect
Column Interconnect
LE0
Fast I/O connection
to IOE
(1)
DirectLink
interconnect from
adjacent LAB
or IOE
LE1
LE2
LE3
LE4
LE5
LE6
DirectLink
interconnect to
adjacent LAB
or IOE
LE7
LE8
LE9
Logic Element
LAB
Local Interconnect
DirectLink
interconnect to
adjacent LAB
or IOE
Fast I/O connection
to IOE
(1)
DirectLink
interconnect from
adjacent LAB
or IOE
Note to
Figure 2–3:
(1)
Only from LABs adjacent to IOEs.
Altera Corporation
March 2008
2–5
MAX II Device Handbook, Volume 1