FLEX 6000 Programmable Logic Device Family Data Sheet
Table 23. External Timing Parameters
Symbol
Parameter
Conditions
tINSU
Setup time with global clock at LE register
Hold time with global clock at LE register
(8)
(8)
tINH
tOUTCO
Clock-to-output delay with global clock with LE register using FastFLEX I/O (8)
pin
Notes to tables:
(1) Microparameters are timing delays contributed by individual architectural elements and cannot be measured
explicitly.
(2) Operating conditions:
V
V
V
= 5.0 V 5% for commercial use in 5.0-V FLEX 6000 devices.
= 5.0 V 10% for industrial use in 5.0-V FLEX 6000 devices.
= 3.3 V 10% for commercial or industrial use in 3.3-V FLEX 6000 devices.
CCIO
CCIO
CCIO
(3) Operating conditions:
V
V
= 3.3 V 10% for commercial or industrial use in 5.0-V FLEX 6000 devices.
= 2.5 V 0.2 V for commercial or industrial use in 3.3-V FLEX 6000 devices.
CCIO
CCIO
(4) Operating conditions:
= 2.5 V, 3.3 V, or 5.0 V.
V
CCIO
(5) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
(6) This timing parameter shows the delay of a register-to-register test pattern and is used to determine speed grades.
There are 12 LEs, including source and destination registers. The row and column interconnects between the
registers vary in length.
(7) This timing parameter is shown for reference and is specified by characterization.
(8) This timing parameter is specified by characterization.
Tables 24 through 28 show the timing information for EPF6010A and
EPF6016A devices.
Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 1 of 2)
Parameter
Speed Grade
-2
Unit
-1
-3
Min
Max
Min
Max
Min
Max
tREG_TO_REG
tCASC_TO_REG
tCARRY_TO_REG
tDATA_TO_REG
tCASC_TO_OUT
tCARRY_TO_OUT
tDATA_TO_OUT
tREG_TO_OUT
tSU
1.2
0.9
0.9
1.1
1.3
1.6
1.7
0.4
1.3
1.0
1.0
1.2
1.4
1.8
2.0
0.4
1.7
1.2
1.2
1.5
1.8
2.3
2.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.9
1.4
1.0
1.7
1.3
2.1
tH
40
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