FLEX 6000 Programmable Logic Device Family Data Sheet
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Powerful I/O pins
...and More
Features
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Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
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Fast path from register to I/O pin for fast clock-to-output time
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Flexible interconnect
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FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
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Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
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Dedicated cascade chain that implements high-speed, high-fan-
in logic functions (automatically used by software tools and
megafunctions)
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Tri-state emulation that implements internal tri-state networks
Four low-skew global paths for clock, clear, preset, or logic
signals
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Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs, Sun
SPARCstations, and HP 9000 Series 700/800
Flexible package options
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Available in a variety of packages with 100 to 256 pins, including
the innovative FineLine BGATM packages (see Table 2)
SameFrameTM pin-compatibility (with other FLEX® 6000 devices)
across device densities and pin counts
Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and
ball-grid array (BGA) packages (see Table 2)
Footprint- and pin-compatibility with other FLEX 6000 devices
in the same package
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Additional design entry and simulation support provided by
EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules
(LPM), Verilog HDL, VHDL, DesignWare components, and other
interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, VeriBest, and Viewlogic
Table 2. FLEX 6000 Package Options & I/O Pin Count
Device
100-Pin
TQFP
100-Pin
FineLine BGA
144-Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
256-Pin
BGA
256-pin
FineLine BGA
EPF6010A
EPF6016
71
102
117
117
117
171
171
171
199
199
204
218
EPF6016A
EPF6024A
81
81
171
219
2
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