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EPF6016TC144-2 参数 Datasheet PDF下载

EPF6016TC144-2图片预览
型号: EPF6016TC144-2
PDF下载: 下载PDF文件 查看货源
内容描述: [Loadable PLD, CMOS, PQFP144, TQFP-144]
分类和应用: 时钟LTE输入元件可编程逻辑
文件页数/大小: 52 页 / 374 K
品牌: ALTERA [ ALTERA CORPORATION ]
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FLEX 6000 Programmable Logic Device Family Data Sheet  
Figure 6. Cascade Chain Operation  
AND Cascade Chain  
OR Cascade Chain  
LE 2  
LE 2  
LE 3  
d[3..0]  
d[7..4]  
d[3..0]  
LUT  
LUT  
LUT  
LUT  
LE 3  
d[7..4]  
LEn + 1  
LE n + 1  
d[(4n-1)..4(n-1)]  
LUT  
d[(4n-1)..4(n-1)]  
LUT  
LE Operating Modes  
The FLEX 6000 LE can operate in one of the following three modes:  
Normal mode  
Arithmetic mode  
Counter mode  
Each of these modes uses LE resources differently. In each mode, seven  
available inputs to the LE—the four data inputs from the LAB local  
interconnect, the feedback from the programmable register, and the  
carry-in and cascade-in from the previous LE—are directed to different  
destinations to implement the desired logic function. LAB-wide signals  
provide clock, asynchronous clear, synchronous clear, and synchronous  
load control for the register. The Altera software, in conjunction with  
parameterized functions such as LPM and DesignWare functions,  
automatically chooses the appropriate mode for common functions such  
as counters, adders, and multipliers. If required, the designer can also  
create special-purpose functions to use an LE operating mode for optimal  
performance.  
Figure 7 shows the LE operating modes.  
Altera Corporation  
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