FLEX 6000 Programmable Logic Device Family Data Sheet
Tables 19 through 21 describe the FLEX 6000 internal timing
microparameters, which are expressed as worst-case values. Using hand
calculations, these parameters can be used to estimate design
performance. However, before committing designs to silicon, actual
worst-case performance should be modeled using timing simulation and
timing analysis. Tables 22 and 23 describe FLEX 6000 external timing
parameters.
Table 19. LE Timing Microparameters
Note (1)
Parameter
Symbol
Conditions
tREG_TO_REG
tCASC_TO_REG
tCARRY_TO_REG
tDATA_TO_REG
tCASC_TO_OUT
tCARRY_TO_OUT
tDATA_TO_OUT
tREG_TO_OUT
tSU
LUT delay for LE register feedback in carry chain
Cascade-in to register delay
Carry-in to register delay
LE input to register delay
Cascade-in to LE output delay
Carry-in to LE output delay
LE input to LE output delay
Register output to LE output delay
LE register setup time before clock; LE register recovery time after
asynchronous clear
tH
LE register hold time after clock
LE register clock-to-output delay
LE register clear delay
tCO
tCLR
tC
LE register control signal delay
Synchronous load or clear delay in counter mode
tLD_CLR
tCARRY_TO_CARRY Carry-in to carry-out delay
tREG_TO_CARRY Register output to carry-out delay
tDATA_TO_CARRY LE input to carry-out delay
tCARRY_TO_CASC Carry-in to cascade-out delay
tCASC_TO_CASC
tREG_TO_CASC
tDATA_TO_CASC
tCH
Cascade-in to cascade-out delay
Register-out to cascade-out delay
LE input to cascade-out delay
LE register clock high time
tCL
LE register clock low time
38
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