FLEX 6000 Programmable Logic Device Family Data Sheet
Table 10. JTAG Timing Parameters & Values
Symbol
Parameter
Min
Max
Unit
tJCP
tJCH
tJCL
TCK clock period
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock high time
TCK clock low time
50
tJPSU JTAG port setup time
tJPH JTAG port hold time
20
45
tJPCO JTAG port clock-to-output
25
25
25
tJPZX JTAG port high impedance to valid output
tJPXZ JTAG port valid output to high impedance
tJSSU Capture register setup time
20
45
tJSH
Capture register hold time
tJSCO Update register clock-to-output
35
35
tJSZX Update register high impedance to valid
output
tJSXZ Update register valid output to high
35
ns
impedance
Each FLEX 6000 device is functionally tested. Complete testing of each
configurable SRAM bit and all logic functionality ensures 100%
configuration yield. AC test measurements for FLEX 6000 devices are
made under conditions equivalent to those shown in Figure 17. Multiple
test patterns can be used to configure devices during all stages of the
production flow.
Generic Testing
Figure 17. AC Test Conditions
Power supply transients can affect
AC measurements. Simultaneous
transitions of multiple outputs
VCC
should be avoided for accurate
464 Ω
(703 Ω)
[521 Ω]
measurement. Threshold tests must
not be performed under AC conditions.
Large-amplitude, fast-ground-current
transients normally occur as the
device outputs discharge the load
capacitances. When these transients
flow through the parasitic
Device
Output
To Test
System
inductance between the device
250 Ω
(8.06 kΩ)
[481 Ω]
ground pin and the test system ground,
significant reductions in observable
noise immunity can result. Numbers
without parentheses are for 5.0-V
devices or outputs. Numbers in
parentheses are for 3.3-V devices or
outputs. Numbers in brackets are for
2.5-V devices or outputs.
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
30
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