FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 18 shows the timing requirements for the JTAG signals.
Figure 18. JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 16 shows the timing parameters and values for FLEX 10K devices.
Table 16. JTAG Timing Parameters & Values
Symbol
Parameter
Min Max Unit
tJCP
tJCH
tJCL
TCKclock period
TCKclock high time
TCKclock low time
100
50
50
20
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJPSU JTAG port setup time
tJPH JTAG port hold time
tJPCO JTAG port clock to output
25
25
25
tJPZX JTAG port high impedance to valid output
tJPXZ JTAG port valid output to high impedance
tJSSU Capture register setup time
20
45
tJSH
Capture register hold time
tJSCO Update register clock to output
35
35
35
tJSZX Update register high-impedance to valid output
tJSXZ Update register valid output to high impedance
Altera Corporation
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