Device Configuration
Page 7
The EPC2 device’s
OE
and
nCS
pins have internal programmable pull-up resistors. If
you use internal pull-up resistors, do not use external pull-up resistors on these pins.
The internal pull-up resistors are set by default in the Quartus II software. To turn off
the internal pull-up resistors, check the
Disable nCS and OE pull-ups on
configuration device
option when you generate programming files.
The configuration device’s
OE
and
nCS
pins control the tri-state buffer on its
DATA
output pin and enable the address counter and oscillator. When the
OE
pin is driven
low, the configuration device resets the address counter and tri-states its
DATA
pin. The
nCS
pin controls the
DATA
output of the configuration device. If the
nCS
pin is held high
after the
OE
reset pulse, the counter is disabled and the
DATA
output pin is tri-stated. If
the
nCS
pin is driven low after the
OE
reset pulse, the counter and
DATA
output pin are
enabled. When
OE
is driven low again, the address counter is reset and the
DATA
output pin is tri-stated, regardless of the state of the
nCS
pin.
If the FPGA’s configuration data exceeds the capacity of a single EPC1 or EPC2
configuration device, you can cascade multiple EPC1 or EPC2 devices together. If
multiple EPC1 or EPC2 devices are required, the
nCASC
and
nCS
pins provide
handshaking between the configuration devices.
1
EPC1441 and EPC1064/EPC1064V devices cannot be cascaded.
When configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II,
FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices with
cascaded EPC1 or EPC2 devices, the position of the EPC1 or EPC2 device in the chain
determines its mode of operation. The first configuration device in the chain is the
master, while subsequent configuration devices are slaves. The
nINIT_CONF
pin of the
EPC2 master device can be connected to the
nCONFIG
pin of the FPGAs, which allows
the
INIT_CONF
JTAG instruction to begin FPGA configuration. The
nCS
pin of the
master configuration device is connected to the
CONF_DONE
pin of the FPGAs, while its
nCASC
pin is connected to the
nCS
pin of the next slave configuration device in the
chain. Additional EPC1 or EPC2 devices can be chained together by connecting the
nCASC
pin to the
nCS
pin of the next EPC1 or EPC2 slave device in the chain. The last
device’s
nCS
input comes from the previous device, while its
nCASC
pin is left floating.
All other configuration pins,
DCLK, DATA,
and
OE,
are connected to every device in the
chain.
f
For more information about configuration interface connections, including pull-up
resistor values, supply voltages, and
MSEL
pin setting, refer to the configuration
chapter in the appropriate device handbook.
January 2012
Altera Corporation
Configuration Devices for SRAM-Based LUT Devices
ALTERA [ ALTERA CORPORATION ]
