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EP3C5E144C8N 参数 Datasheet PDF下载

EP3C5E144C8N图片预览
型号: EP3C5E144C8N
PDF下载: 下载PDF文件 查看货源
内容描述: 能够禁用外部JTAG端口 [Ability to disable external JTAG port]
分类和应用: 现场可编程门阵列可编程逻辑PC时钟
文件页数/大小: 348 页 / 6766 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–24  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
PLL Cascading  
Figure 5–18 shows an example of phase shift insertion using fine resolution through  
VCO phase taps method. The eight phases from the VCO are shown and labeled for  
reference. In this example, CLK0is based on 0° phase from the VCO and has the C  
value for the counter set to one. The CLK1signal is divided by four, two VCO clocks  
for high time and two VCO clocks for low time. CLK1is based on the 135° phase tap  
from the VCO and has the C value for the counter set to one. The CLK1signal is also  
divided by four. In this case, the two clocks are offset by 3 Φfine. CLK2is based on the  
0° phase from the VCO but has the C value for the counter set to three. This creates a  
delay of two Φcoarse (two complete VCO periods).  
Figure 5–18. Delay Insertion Using VCO Phase Output and Counter Delay Time  
1/8 t  
t
VCO  
VCO  
0
45  
90  
135  
180  
225  
270  
315  
CLK0  
t
d0-1  
CLK1  
CLK2  
t
d0-2  
You can use the coarse and fine phase shifts to implement clock delays in the  
Cyclone III device family.  
The Cyclone III device family supports dynamic phase shifting of VCO phase taps  
only. The phase shift is configurable for any number of times. Each phase shift takes  
about one scanclkcycle, allowing you to implement large phase shifts quickly.  
PLL Cascading  
Two PLLs are cascaded to each other through the clock network. If your design  
cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while  
the destination (downstream) PLL must have a high-bandwidth setting.  
Cyclone III Device Handbook  
Volume 1  
December 2011 Altera Corporation