9–54
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–27. JTAG Configuration of Multiple Devices Using a Download Cable (1.2, 1.5, and 1.8-V VCCIO Powering the
JTAG Pins)
Download Cable
10-Pin Male Header
(1)
(1)
(1)
(1)
V
CCIO
V
CCIO
(1)
(1)
V
CCIO
V
CCIO
V
CCIO (1)
V
CCIO
V
CCIO
Cyclone III
Device Family
Cyclone III
Device Family
Cyclone III
Device Family
10 kΩ
10 kΩ
nST
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
10 kΩ
10 kΩ
10 kΩ
10 kΩ
(6)
Pin 1
V
CCIO (5)
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
A
TUS
V
CCIO (1)
nSTATUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(6)
CONF_DONE
CONF_DONE
CONF_DONE
(2)
(2)
(2)
VIO
(3)
nCE (4)
nCE (4)
nCE (4)
TDI
TDI
TDO
TDI
TDO
TDO
TCK
TMS
TCK
TMS
TCK
TMS
1 kΩ
Notes to Figure 9–27:
(1) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the nCONFIGand MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the
nCONFIGpin to logic high and the MSEL[3..0]pins to ground. In addition, pull DCLKand DATA[0] either high or low, whichever is convenient
on your board.
(3) In the USB-Blaster and ByteBlaster II cable, this pin is connected to nCEwhen it is used for AS programming, otherwise it is a no connect.
(4) The nCEpin must be connected to ground or driven low for successful JTAG configuration.
(5) Power up the VCC of the ByteBlaster II or USB-Blaster cable with supply from VCCIO. The ByteBlaster II and USB-Blaster cables do not support a
target supply voltage of 1.2 V. For the target supply voltage value, refer to the ByteBlaster II Download Cable User Guide and the USB-Blaster
Download Cable User Guide.
(6) The resistor value can vary from 1 kΩ to 10 kΩ. Perform signal integrity analysis to select the resistor value for your setup.
1
All I/O inputs must maintain a maximum AC voltage of 4.1 V. If a non-Cyclone III
device family is cascaded in the JTAG-chain, TDOof the non-Cyclone III device family
driving into TDIof the Cyclone III device family must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
The nCEpin must be connected to GND or driven low during JTAG configuration. In
multi-device AS, AP, PS, and FPP configuration chains, the nCEpin of the first device
is connected to GND while its nCEOpin is connected to the nCEpin of the next device
in the chain. The inputs of the nCEpin of the last device come from the previous device
while its nCEOpin is left floating. In addition, the CONF_DONEand nSTATUSsignals are
shared in multi-device AS, AP, PS, and FPP configuration chains to ensure that the
devices enter user mode at the same time after configuration is complete. When the
CONF_DONEand nSTATUSsignals are shared among all the devices, every device must
be configured when you perform JTAG configuration.
If you only use JTAG configuration, Altera recommends that you connect the circuitry
as shown in Figure 9–26 or Figure 9–27, in which each of the CONF_DONEand nSTATUS
signals are isolated so that each device can enter user mode individually.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
