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EP3C5E144C8N 参数 Datasheet PDF下载

EP3C5E144C8N图片预览
型号: EP3C5E144C8N
PDF下载: 下载PDF文件 查看货源
内容描述: 能够禁用外部JTAG端口 [Ability to disable external JTAG port]
分类和应用: 现场可编程门阵列可编程逻辑PC时钟
文件页数/大小: 348 页 / 6766 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 6: I/O Features in the Cyclone III Device Family  
6–15  
Termination Scheme for I/O Standards  
Differential I/O Standard Termination  
Differential I/O standards typically require a termination resistor between the two  
signals at the receiver. The termination resistor must match the differential load  
impedance of the bus (Figure 6–8 and Figure 6–9).  
The Cyclone III device family supports differential SSTL-2 and SSTL-18, differential  
HSTL-18, HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and  
differential LVPECL.  
Figure 6–8. Cyclone III Device Family Differential HSTL I/O Standard Termination  
Termination  
Differential HSTL  
V
V
TT  
TT  
External  
On-Board  
Termination  
Receiver  
Transmitter  
V
V
TT  
TT  
Cyclone III Device  
Family Series OCT  
50  
OCT  
Transmitter  
Receiver  
(1)  
Figure 6–9. Cyclone III Device Family Differential SSTL I/O Standard Termination  
Termination  
Differential SSTL Class I  
Differential SSTL Class II  
V
V
V
V
TT TT  
TT TT  
V
V
TT  
TT  
50  
25   
50   
50   
50   
50   
50   
50   
25   
25   
50   
External  
On-Board  
Termination  
25   
50   
50  
Transmitter  
Receiver  
Transmitter  
Receiver  
V
V
TT  
V
V
TT  
V
V
TT  
TT  
TT  
TT  
Cyclone III Device  
Family Series OCT  
50  
Cyclone III Device  
Family Series OCT  
25   
50 50 50 50   
50   
50   
50   
50   
OCT  
50   
50   
Transmitter  
Receiver  
Transmitter  
Receiver  
Note to Figure 6–9:  
(1) Only Differential SSTL-2 I/O standard supports Class II output.  
December 2011 Altera Corporation  
Cyclone III Device Handbook  
Volume 1