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EP3C5E144C8N 参数 Datasheet PDF下载

EP3C5E144C8N图片预览
型号: EP3C5E144C8N
PDF下载: 下载PDF文件 查看货源
内容描述: 能够禁用外部JTAG端口 [Ability to disable external JTAG port]
分类和应用: 现场可编程门阵列可编程逻辑PC时钟
文件页数/大小: 348 页 / 6766 K
品牌: ALTERA [ ALTERA CORPORATION ]
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6–8  
Chapter 6: I/O Features in the Cyclone III Device Family  
OCT Support  
On-Chip Series Termination with Calibration  
The Cyclone III device family supports on-chip series termination with calibration in  
all banks. The on-chip series termination calibration circuit compares the total  
impedance of the output buffer to the external 25-Ω 1% or 50-Ω 1% resistors  
connected to the RUPand RDNpins, and dynamically adjusts the output buffer  
impedance until they match (as shown in Figure 6–2).  
The RS shown in Figure 6–2 is the intrinsic impedance of the transistors that make up  
the output buffer.  
Figure 6–2. Cyclone III Device Family On-Chip Series Termination with Calibration  
Cyclone III Device Family  
Driver Series Termination  
Receiving  
Device  
V
CCIO  
R
S
Z
O
R
S
GND  
OCT with calibration is achieved using the OCT calibration block circuitry. There is  
one OCT calibration block in banks 2, 4, 5, and 7. Each calibration block supports each  
side of the I/O banks. Because there are two I/O banks sharing the same calibration  
block, both banks must have the same VCCIO if both banks enable OCT calibration. If  
two related banks have different VCCIOs, only the bank in which the calibration block  
resides can enable OCT calibration.  
Cyclone III Device Handbook  
Volume 1  
December 2011 Altera Corporation