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EP3C5E144C8N 参数 Datasheet PDF下载

EP3C5E144C8N图片预览
型号: EP3C5E144C8N
PDF下载: 下载PDF文件 查看货源
内容描述: 能够禁用外部JTAG端口 [Ability to disable external JTAG port]
分类和应用: 现场可编程门阵列可编程逻辑PC时钟
文件页数/大小: 348 页 / 6766 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 6: I/O Features in the Cyclone III Device Family  
6–3  
I/O Element Features  
Table 6–1 lists the possible settings for I/O standards with current strength control.  
These programmable current strength settings are a valuable tool in helping decrease  
the effects of simultaneously switching outputs (SSO) in conjunction with reducing  
system noise. The supported settings ensure that the device driver meets the  
specifications for IOHand IOLof the corresponding I/O standard.  
1
When you use programmable current strength, on-chip series termination is not  
available.  
(1)  
Table 6–1. Programmable Current Strength  
IOH/IOL Current Strength Setting (mA)  
I/O Standard  
Top and Bottom I/O Pins  
Left and Right I/O Pins  
1.2-V LVCMOS  
2, 4, 6, 8, 10,12  
2, 4, 6, 8,10  
1.5-V LVCMOS  
2, 4, 6, 8, 10, 12,16  
2, 4, 6, 8, 10, 12,16  
1.8-V LVTTL/LVCMOS  
2.5-V LVTTL/LVCMOS  
3.0-V LVCMOS  
2, 4, 6, 8, 10, 12,16  
4, 8, 12,16  
4, 8, 12,16  
4, 8, 12,16  
2
2, 4, 6, 8, 10, 12,16  
4, 8, 12,16  
4, 8, 12,16  
4, 8, 12,16  
2
3.0-V LVTTL  
(2)  
3.3-V LVCMOS  
(2)  
3.3-V LVTTL  
4, 8  
4, 8  
HSTL-12 Class I  
HSTL-12 Class II  
HSTL-15 Class I  
HSTL-15 Class II  
HSTL-18 Class I  
HSTL-18 Class II  
SSTL-18 Class I  
SSTL-18 Class II  
SSTL-2 Class I  
SSTL-2 Class II  
BLVDS  
8, 10,12  
14  
8, 10  
8, 10, 12  
16  
8, 10, 12  
16  
8, 10, 12  
16  
8, 10, 12  
16  
8, 10, 12  
12, 16  
8, 10, 12  
12, 16  
8, 12  
8, 12  
16  
16  
8, 12, 16  
8, 12, 16  
Notes to Table 6–1:  
(1) The default setting in the Quartus II software is 50-Ω OCT without calibration for all non-voltage reference and  
HSTL/SSTL Class I I/O standards. The default setting is 25-Ω OCT without calibration for HSTL/SSTL Class II I/O  
standards.  
(2) The default current setting in the Quartus II software is highlighted in bold italic for 3.3-V LVTTL and 3.3-V LVCMOS  
I/O standards.  
f
For information about how to interface the Cyclone III device family with 3.3-, 3.0-, or  
2.5-V systems, refer to the guidelines provided in AN 447: Interfacing Cyclone III and  
Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.  
December 2011 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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