欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP3C55F484C6N 参数 Datasheet PDF下载

EP3C55F484C6N图片预览
型号: EP3C55F484C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 55856 CLBs, 472.5MHz, 55856-Cell, CMOS, PBGA484, 23 X 23 MM, 2.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 367 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP3C55F484C6N的Datasheet PDF文件第13页浏览型号EP3C55F484C6N的Datasheet PDF文件第14页浏览型号EP3C55F484C6N的Datasheet PDF文件第15页浏览型号EP3C55F484C6N的Datasheet PDF文件第16页浏览型号EP3C55F484C6N的Datasheet PDF文件第18页浏览型号EP3C55F484C6N的Datasheet PDF文件第19页浏览型号EP3C55F484C6N的Datasheet PDF文件第20页浏览型号EP3C55F484C6N的Datasheet PDF文件第21页  
Chapter 1: Cyclone III Device Data Sheet  
1–17  
Switching Characteristics  
Embedded Multiplier Specifications  
Table 1–21 describes the embedded multiplier specifications for Cyclone III devices.  
Table 1–21. Cyclone III Devices Embedded Multiplier Specifications  
Resources Used  
Performance  
C7, I7, A7  
Mode  
9 × 9-bit  
Unit  
Number of Multipliers  
C6  
C8  
1
1
340  
300  
250  
260  
MHz  
MHz  
multiplier  
18 × 18-bit  
multiplier  
287  
200  
Memory Block Specifications  
Table 1–22 describes the M9K memory block specifications for Cyclone III devices.  
Table 1–22. Cyclone III Devices Memory Block Performance Specifications  
Resources Used  
Performance  
Memory  
Mode  
M9K  
LEs  
C6  
C7, I7, A7  
C8  
Unit  
Memory  
FIFO 256 × 36  
47  
0
1
1
1
1
315  
315  
315  
315  
274  
274  
274  
274  
238  
238  
238  
238  
MHz  
MHz  
MHz  
MHz  
Single-port 256 × 36  
M9K Block  
Simple dual-port 256 × 36 CLK  
True dual port 512 × 18 single CLK  
0
0
Configuration and JTAG Specifications  
Table 1–23 lists the configuration mode specifications for Cyclone III devices.  
Table 1–23. Cyclone III Devices Configuration Mode Specifications  
Programming Mode  
Passive Serial (PS)  
DCLK Fm ax  
133  
Unit  
MHz  
MHz  
Fast Passive Parallel (FPP) (1)  
100  
Note to Table 1–23:  
(1) EP3C40 and smaller density members support 133 MHz.  
Table 1–24 lists the active configuration mode specifications for Cyclone III devices.  
Table 1–24. Cyclone III Devices Active Configuration Mode Specifications  
Programming Mode  
Active Parallel (AP)  
Active Serial (AS)  
DCLK Range  
20 – 40  
Unit  
MHz  
MHz  
20 – 40  
© January 2010 Altera Corporation  
Cyclone III Device Handbook, Volume 2  
 
 
 
 
 
 复制成功!