5–6
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
GCLK Network Clock Source Generation
shows Cyclone III device family PLLs, clock inputs, and clock control
block location for different device densities.
Figure 5–2. PLL, CLK[], DPCLK[], and Clock Control Block Locations in the Cyclone III Device Family
DPCLK[11.10]
CDPCLK7
2
DPCLK[9..8]
CDPCLK6
CLK[11..8]
4
2
(3)
4
5
4
PLL
3
CDPCLK0
(3)
(2)
PLL
2
CDPCLK5
(2)
2
4
2
GCLK[19..0]
DPCLK0
20
4
20
DPCLK1
Clock Control
Block
(1)
4
5
(2)
CDPCLK1
5
PLL
1
(3)
4
2
CDPCLK2
CLK[15..12]
DPCLK[3..2]
DPCLK[5..4]
4
2
CDPCLK3
4
2
(2)
GCLK[19..0]
2
20
20
Clock Control
Block
(1)
5
4
DPCLK7
CLK[3..0]
4
CLK[7..4]
DPCLK6
4
(3)
CDPCLK4
PLL
4
Notes to
(1) There are five clock control blocks on each side.
(2) Only one of the corner
CDPCLK
pins in each corner can feed the clock control block at a time. You can use the other
CDPCLK
pins as
general-purpose I/O pins.
(3) Remote clock pins can feed PLLs over dedicated clock paths. However, these paths are not fully compensated.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
