Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–51
Configuration Features
Figure 9–25. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V VCCIO
Powering the JTAG Pins)
V
CCIO
(1)
V
(2)
CCIO
V
CCIO
10 kΩ
V
(2)
CCIO
(1)
Cyclone III Device Family
10 kΩ
nCE (3)
TCK
TDO
GND
N.C. (4)
nCEO
TMS
TDI
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
DATA[0]
Download Cable
10-Pin Male Header (Top View)
(5)
(5)
(5)
(5)
Pin 1
V
(6)
CCIO
DCLK
GND
(7)
V
IO
1 kΩ
GND
GND
Notes to Figure 9–25:
(1) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your
setup.
(2) Connect these pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(3) The nCEmust be connected to GND or driven low for successful JTAG configuration.
(4) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(5) Connect the nCONFIGand MSEL[3..0]pins to support a non-JTAG configuration scheme. If you only use a JTAG
configuration, connect the nCONFIGpin to logic-high and the MSEL[3..0]pins to ground. In addition, pull DCLKand
DATA[0]either high or low, whichever is convenient on your board.
(6) Power up the VCC of the ByteBlaster II, USB-Blaster, or Ethernet Blaster cable with supply from VCCIO. The
ByteBlaster II, USB-Blaster, and Ethernet Blaster cables do not support a target supply voltage of 1.2 V. For the target
supply voltage value, refer to the ByteBlaster II Download Cable User Guide, USB-Blaster Download Cable User Guide
and Ethernet Blaster Communications Cable User Guide.
(7) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCEwhen it is used for AS programming;
otherwise it is a no connect.
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDIpin to the TDOpin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDOpin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of CONF_DONEthrough the JTAG
port. When the Quartus II software generates a .jam for a multi-device chain, it
contains instructions to have all devices in the chain initialize at the same time. If
CONF_DONEis not high, the Quartus II software indicates that configuration has failed.
If CONF_DONEis high, the software indicates that configuration was successful. After
the configuration bitstream is serially sent using the JTAG TDIport, the TCKport
clocks an additional clock cycle to perform device initialization.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
