9–26
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
The interface for the Micron P30 flash memory and P33 flash memory connects to
Cyclone III device pins, as shown in Figure 9–8.
Figure 9–8. Single-Device AP Configuration Using Micron P30 and P33 Flash Memory
V
CCIO
(1) V
(1) V (1)
CCIO
CCIO
10k
10k
10k
UTS
A
SnT
CnONFGI
N.C. (2)
(3)
nCEO
FC_DOEN
nCE
GND
MSEL[3..0]
CLK
RST#
CE#
DCLK
nRESET
FLASH_nCE
nOE
OE#
ADV#
WE#
nAVD
nWE
WAIT
I/O (4)
DQ[15:0]
A[24:1]
DATA[15..0]
PADD[23..0]
Micron P30/P33 Flash
Cyclone III Device
Notes to Figure 9–8:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to Table 9–7 on page 9–11.
Connect the MSEL pins directly to VCCA or GND.
(4) The AP configuration ignores the WAITsignal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use a normal I/O to monitor the WAITsignal from the Micron P30 or P33 flash.
1
1
To tri-state the configuration bus for AP configuration schemes, you must tie nCEhigh
and nCONFIGlow.
In a single-device AP configuration, the maximum board loading and board trace
length between the supported parallel flash and Cyclone III devices must follow the
recommendations listed in Table 9–12 on page 9–30.
1
If you use the AP configuration scheme for Cyclone III devices, the VCCIO of I/O
banks 1, 6, 7, and 8 must be 3.3, 3.0, 2.5, or 1.8 V. Altera does not recommend using the
level shifter between the Micron P30/P33 flash and the Cyclone III device in the AP
configuration scheme.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
