Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–19
Configuration Features
Single SRAM Object File
The second method configures both the master device and slave devices with the
same .sof. The serial configuration device stores one copy of the .sof. This setup is
shown in Figure 9–6 where the master is set up in AS mode and the slave devices are
set up in PS mode. You must set up one or more slave devices in the chain. All the
slave devices must be set up as shown in Figure 9–6.
Figure 9–6. Multi-Device AS Configuration where the Devices Receive the Same Data with a Single .sof
V
(1)
V
(1)
V
(1)
CCIO
CCIO
CCIO
10 kΩ
10 kΩ
10 kΩ
Slave Device 2 of the Cyclone III
Slave Device 1 of the Cyclone III
Master Device of the Cyclone III
Serial Configuration
Device Family
Device Family
Device
Device Family
nSTATUS
nSTATUS
nSTATUS
CONF_DONE
nCONFIG
CONF_DONE
nCONFIG
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (2)
GND
nCE
nCEO
N.C. (2)
nCE
nCEO
N.C. (2)
GND
GND
(5)
25 Ω
DATA[0]
DCLK
DATA[0]
DATA
DATA[0]
DCLK
(5),(7)
50 Ω
DCLK
nCS
ASDI
DCLK
nCSO (4)
ASDO (4)
MSEL[3..0]
(3)
MSEL[3..0]
(3)
MSEL[3..0]
(3)
50 Ω(7)
Buffers (6)
Notes to Figure 9–6:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device
family in AS mode and the slave devices in PS mode. To connect MSEL[3..0]for the master device in AS mode and slave devices in PS mode,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.
(4) These are dual-purpose I/O pins. The nCSOpin functions as the FLASH_NCEpin in AP mode. The ASDOpin functions as the DATA[1]pin in other
AP and FPP modes.
(5) Connect the series resistor at the near end of the serial configuration device.
(6) Connect the repeater buffers between the master and slave devices for DATA[0]and DCLK. All I/O inputs must maintain a maximum AC voltage
of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O
Requirements” on page 9–7.
(7) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
In this setup, all the Cyclone III device family in the chain are connected for
concurrent configuration. This can reduce the AS configuration time because all the
Cyclone III device family is configured in one configuration cycle. Connect the nCE
input pins of all the Cyclone III device family to ground. You can either leave the nCEO
output pins on all the Cyclone III device family unconnected or use the nCEOoutput
pins as normal user I/O pins. The DATAand DCLKpins are connected in parallel to all
the Cyclone III device family.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
