Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
5–29
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■
■
High time count = 2 cycles
Low time count = 1 cycle
rselodd
= 1 effectively equals:
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High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Scan Chain Description
Cyclone III device family PLLs have a 144-bit scan chain.
lists the number of bits for each component of the PLL.
Table 5–4. Cyclone III Device Family PLL Reprogramming Bits
Number of Bits
Block Name
Counter
C4
C3
C2
C1
C0
M
N
Charge Pump
Loop Filter
Other
2
2
2
2
2
2
2
Total
18
18
18
18
18
18
18
9
9
144
16
16
16
16
16
16
16
9
9
0
0
Total number of bits:
Notes to
(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.
(2) These two control bits include
rbypass,
for bypassing the counter, and
rselodd,
to select the output clock duty
cycle.
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
shows the scan chain order of the PLL components.
Figure 5–22. PLL Component Scan Chain Order
DATAIN
LF
MSB
CP
LSB
N
M
C0
DATAOUT
C4
C3
C2
C1
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
