3–2
Chapter 3: Memory Blocks in the Cyclone III Device Family
Overview
lists the features supported by the M9K memory
Table 3–1. Summary of M9K Memory Features
Feature
M9K Blocks
8192 × 1
4096 × 2
2048 × 4
1024 × 8
Configurations (depth × width)
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port mode
Simple dual-port mode
True dual-port mode
Embedded shift register mode
ROM mode
FIFO buffer
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Outputs cleared
Read address registers and output registers only
Output latches only
Write and read: Rising clock edges
Outputs set to
Old Data
or
New Data
Outputs set to
Old Data
or
Don’t Care
Simple dual-port mixed width support
True dual-port mixed width support
Memory initialization file (.mif)
Mixed-clock mode
Power-up condition
Register asynchronous clears
Latch asynchronous clears
Write or read operation triggering
Same-port read-during-write
Mixed-port read-during-write
Notes to
(1) FIFO buffers and embedded shift registers that require external logic elements (LEs) for implementing control
logic.
(2) Width modes of ×32 and ×36 are not available.
f
For information about the number of M9K memory blocks for the Cyclone III device
family, refer to the
chapter.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
