8–14
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Document Revision History
1
The PLL is instantiated in the ALTMEMPHY megafunction. All outputs of the PLL are
used when the ALTMEMPHY megafunction is instantiated to interface with external
memories.
f
For more information about the usage of PLL outputs by the ALTMEMPHY
megafunction, refer to the
page.
f
For more information about Cyclone III device family PLL, refer to the
chapter.
Document Revision History
lists the revision history for this document.
Table 8–3. Document Revision History
Date
July 2012
Version
3.1
Finalized
■
Changes
Updated “Data and Data Clock/Strobe Pins” on page 8–2 and “Memory Clock Pins” on
page 8–10.
Updated hyperlinks.
Minor text edits.
Removed Tables 8-1, 8-2, 8-3, and 8-4.
Changed links to reference
Literature: External Memory Interfaces.
December 2011
3.0
■
■
January 2010
December 2009
July 2009
2.3
2.2
2.1
■
■
Minor changes to the text.
Made minor correction to the part number.
■
■
■
Updated chapter part number.
Updated “Introduction” on page 8–1.
Updated Table 8–1 on page 8–1, Table 8–2 on page 8–2, Table 8–3 on page 8–3,
Table 8–4 on page 8–4, and Table 8–5 on page 8–7. Updated notes to Table 8–6 on
page 8–10. Updated “Data and Data Clock/Strobe Pins” on page 8–5.
Updated note to Figure 8–2 on page 8–12.
Updated “Optional Parity, DM, and Error Correction Coding Pins” on page 8–13.
Updated “Address and Control/Command Pins” on page 8–14.
Updated “Introduction”, “DDR Input Registers” and “Conclusion” sections.
Updated chapter to new template.
Added
(Note 4)
to Figure 8–3.
Updated Table 8–3 and Table 8-5. Added new Table 8–4.
Updated
(Note 1)
to Figure 8-4. Updated Figure 8–5 and 8–14.
Updated “Data and Data Clock/Strobe Pins” section.
Updated Table 8–5.
Added chapter TOC and “Referenced Documents” section.
June 2009
2.0
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October 2008
1.3
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■
■
May 2008
1.2
■
■
■
July 2007
March 2007
1.1
1.0
■
■
Initial release.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation