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EP3C16Q144C6ES 参数 Datasheet PDF下载

EP3C16Q144C6ES图片预览
型号: EP3C16Q144C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7308 K
品牌: ALTERA [ ALTERA CORPORATION ]
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7–16
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Timing
High-Speed I/O Timing
This section discusses the timing budget, waveforms, and specifications for
source-synchronous signaling in the Cyclone III device family. Timing for
source-synchronous signaling is based on skew between the data and clock signals.
High-speed differential data transmission requires timing parameters provided by IC
vendors and requires you to consider the board skew, cable skew, and clock jitter. This
section provides information about high-speed I/O standards timing parameters in
the Cyclone III device family.
lists the parameters of the timing diagram as shown in
Table 7–5. High-Speed I/O Timing Definitions
Parameter
Transmitter channel-to-channel skew
Symbol
TCCS
Description
The timing difference between the fastest and slowest output
edges, including t
CO
variation and clock skew. The clock is
included in the TCCS measurement.
The period of time during which the data must be valid in order
for you to capture it correctly. The setup and hold times
determine the ideal strobe position in the sampling window.
T
SW
= T
SU
+ T
hd
+ PLL jitter.
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS. The RSKM equation is:
RSKM
=
TUI
SW
TCCS
--------------------------------------------------
2
Sampling window
SW
Receiver input skew margin
RSKM
Input jitter tolerance (peak-to-peak)
Output jitter (peak-to-peak)
Note to
Allowed input jitter on the input clock to the PLL that is tolerable
while maintaining PLL lock.
Peak-to-peak output jitter from the PLL.
(1) The TCCS specification applies to the entire bank of differential I/O as long as the SERDES logic is placed in the logic array block (LAB) adjacent
to the output pins.
Figure 7–15. High-Speed I/O Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal Clock
TCCS
RSKM
Sampling Window (SW)
RSKM
TCCS
Receiver
Input Data
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation