Chapter 6: I/O Features in the Cyclone III Device Family
Pad Placement and DC Guidelines
6–21
Pad Placement and DC Guidelines
Pad Placement
Altera recommends that you create a Quartus II design, enter your device I/O
assignments, and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation. These rules are dependent on
device density, package, I/O assignments, voltage assignments, and other factors that
are not fully described in this chapter.
f
For more information about how the Quartus II software checks I/O restrictions, refer
to the
chapter in volume 2 of the
Quartus II Handbook.
DC Guidelines
For the Quartus II software to automatically check for illegally placed pads according
to the DC guidelines, set the DC current sink or source value to
Electromigration
Current
assignment on each of the output pins that are connected to the external
resistive load.
The programmable current strength setting has an impact on the amount of DC
current that an output pin can source or sink. Determine if the current strength setting
is sufficient for the external resistive load condition on the output pin.
Document Revision History
lists the revision history for this document.
Table 6–7. Document Revision History (Part 1 of 3)
Date
July 2012
Version
3.4
Updated Table 6–1 and Table 6–4.
Updated “Programmable Pull-Up Resistor” on page 6–5, “OCT Support” on page 6–7,
and “I/O Standards” on page 6–11.
Updated hyperlinks.
Minor text edits.
Changes
Updated OCT with or without calibration note in
section,
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December 2011
3.3
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December 2009
July 2009
3.2
3.1
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
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Updated chapter part number.
Updated “Introduction” on page 6–1, “PCI-Clamp Diode” on page 6–6, “On-Chip Series
Termination Without Calibration” on page 6–10, “I/O Standards” on page 6–11, “I/O
Banks” on page 6–16, “High-Speed Differential Interfaces” on page 6–20, and “External
Memory Interfacing” on page 6–20.
Updated Table 6–6 on page 6–18.
June 2009
3.0
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July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
