6–16
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
f
For information about the Cyclone III device family
differential PPDS, LVDS,
mini LVDS, RSDS
I/O, and Bus LVDS (BLVDS) standard termination, refer to the
chapter.
I/O Banks
I/O pins on the Cyclone III device family are grouped together into I/O banks, and
each bank has a separate power bus. Cyclone III and Cyclone III LS devices have eight
I/O banks, as shown in
Each device I/O pin is associated with one I/O
bank. All single-ended I/O standards are supported in all banks except
HSTL-12
Class II,
which is only supported in column I/O banks. All differential I/O standards
are supported in all banks. The only exception is
HSTL-12 Class II,
which is only
supported in column I/O banks.
Figure 6–10. Cyclone III Device Family I/O Banks
I/O Bank 8
I/O Bank 7
All I/O Banks Support:
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
PPDS
LVDS
RSDS
mini-LVDS
Bus LVDS (7)
LVPECL
(3)
SSTL-2 class I and II
SSTL-18 CLass I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II
(4)
Differential SSTL-2
(5)
Differential SSTL-18
(5)
Differential HSTL-18
(5)
Differential HSTL-15
(5)
Differential HSTL-12
(6)
I/O Bank 6
I/O Bank 2
I/O Bank 1
I/O Bank 3
I/O Bank 4
Notes to
(1) This is a top view of the silicon die. This is only a graphical representation. For exact pin locations, refer to the pin list and the Quartus II software.
(2) True differential (PPDS,
LVDS, mini-LVDS,
and
RSDS
I/O standards) outputs are supported in row I/O banks 1, 2, 5, and 6 only. External resistors
are needed for the differential outputs in column I/O banks.
(3) The
LVPECL
I/O standard is only supported on clock input pins. This I/O standard is not supported on output pins.
(4) The
HSTL-12 Class II
is supported in column I/O banks 3, 4, 7, and 8 only.
(5) The
differential SSTL-18
and
SSTL-2, differential HSTL-18,
and
HSTL-15
I/O standards are supported only on clock input pins and phase-locked
loops (PLLs) output clock pins.
Differential SSTL-18, differential HSTL-18,
and
HSTL-15
I/O standards do not support Class II output.
(6) The
differential HSTL-12
I/O standard is only supported on clock input pins and PLL output clock pins.
Differential HSTL-12 Class II
is supported
only in column I/O banks 3, 4, 7, and 8.
(7)
BLVDS
output uses two single-ended outputs with the second output programmed as inverted.
BLVDS
input uses the
LVDS
input buffer.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
I/O Bank 5
ALTERA [ ALTERA CORPORATION ]
