Chapter 1: Cyclone III Device Datasheet
1–19
Switching Characteristics
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 2 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
55
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
55
Min
100
80
Typ
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
55
×10
×8
×7
×4
×2
×1
—
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
Device
operation in
Mbps
70
70
70
40
40
40
20
20
20
10
10
10
tDUTY
45
45
45
TCCS
—
200
—
200
—
200
ps
Output jitter
(peak to
peak)
—
—
—
—
500
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%,
tRISE
500
500
500
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(2)
tLOCK
ms
Notes to Table 1–27:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 1 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
200
200
200
200
200
400
400
400
400
400
400
400
55
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
f
HSCLK (input
clock
frequency)
5
5
5
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
311
100
80
70
40
20
10
45
—
311
311
311
Device
operation in
Mbps
311
311
311
311
311
311
311
311
tDUTY
55
55
TCCS
200
200
200
ps
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
ALTERA [ ALTERA CORPORATION ]
