PLLs & Clock Networks
Enhanced PLLs
Stratix II devices contain up to four enhanced PLLs with advanced clock
management features. Figure 2–44 shows a diagram of the enhanced PLL.
Figure 2–44. Stratix II Enhanced PLL Note (1)
From Adjacent PLL
Post-Scale
VCO Phase Selection
Selectable at Each
PLL Output Port
Counters
Clock
Switchover
Circuitry
Spread
Spectrum
/c0
/c1
/c2
Phase Frequency
Detector
INCLK[3..0]
4
4
8
6
Global
Clocks
/n
8
Charge
Pump
Loop
Filter
PFD
VCO
6
Regional
Clocks
Global or
Regional
/c3
/c4
/c5
Clock
(4)
I/O Buffers
(3)
/m
(2)
to I/O or general
routing
Lock Detect
& Filter
FBIN
VCO Phase Selection
Affecting All Outputs
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–44:
(1) Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
(2) If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
(3) Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
2–68
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
