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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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TriMatrix Memory  
Table 2–2. Stratix II Device Routing Scheme (Part 2 of 2)  
Destination  
Source  
Column IOE  
v
v
v
v
Row IOE  
v
v
v
TriMatrix memory consists of three types of RAM blocks: M512, M4K,  
and M-RAM. Although these memory blocks are different, they can all  
implement various types of memory with or without parity, including  
true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO  
buffers. Table 2–3 shows the size and features of the different RAM  
blocks.  
TriMatrix  
Memory  
Table 2–3. TriMatrix Memory Features (Part 1 of 2)  
M512 RAM Block  
Memory Feature  
M4K RAM Block  
(128 × 36 Bits)  
M-RAM Block  
(4K × 144 Bits)  
(32 × 18 Bits)  
Maximum performance  
True dual-port memory  
Simple dual-port memory  
Single-port memory  
Shift register  
500 MHz  
550 MHz  
v
420 MHz  
v
v
v
v
v
v
v
v
v
v
v
ROM  
(1)  
v
v
v
v
v
v
v
FIFO buffer  
v
Pack mode  
v
Byte enable  
v
v
Address clock enable  
Parity bits  
v
v
v
v
v
Mixed clock mode  
Memory initialization (.mif)  
v
v
2–28  
Altera Corporation  
May 2007  
Stratix II Device Handbook, Volume 1  
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