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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
C16 column interconnects span a length of 16 LABs and provide the  
fastest resource for long column connections between LABs, TriMatrix  
memory blocks, DSP blocks, and IOEs. C16 interconnects can cross  
M-RAM blocks and also drive to row and column interconnects at every  
fourth LAB. C16 interconnects drive LAB local interconnects via C4 and  
R4 interconnects and do not drive LAB local interconnects directly.  
All embedded blocks communicate with the logic array similar to LAB-  
to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)  
connects to row and column interconnects and has local interconnect  
regions driven by row and column interconnects. These blocks also have  
direct link interconnects for fast connections to and from a neighboring  
LAB. All blocks are fed by the row LAB clocks, labclk[5..0].  
Table 2–2 shows the Stratix II device’s routing scheme.  
Table 2–2. Stratix II Device Routing Scheme (Part 1 of 2)  
Destination  
Source  
Shared arithmetic chain  
Carry chain  
v
v
v
v
Register chain  
Local interconnect  
Direct link interconnect  
R4 interconnect  
R24 interconnect  
C4 interconnect  
C16 interconnect  
ALM  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
M512 RAM block  
M4K RAM block  
M-RAM block  
v
DSP blocks  
Altera Corporation  
May 2007  
2–27  
Stratix II Device Handbook, Volume 1  
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