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EP2S90F1020C4N 参数 Datasheet PDF下载

EP2S90F1020C4N图片预览
型号: EP2S90F1020C4N
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix II系列提供了以下功能 [The Stratix II family offers the following features]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 238 页 / 2897 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
The Quartus II Compiler automatically creates carry chain logic during  
design processing, or you can create it manually during design entry.  
Parameterized functions such as LPM functions automatically take  
advantage of carry chains for the appropriate functions.  
The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in  
arithmetic or shared arithmetic mode) by linking LABs together  
automatically. For enhanced fitting, a long carry chain runs vertically  
allowing fast horizontal connections to TriMatrix memory and DSP  
blocks. A carry chain can continue as far as a full column.  
To avoid routing congestion in one small area of the device when a high  
fan-in arithmetic function is implemented, the LAB can support carry  
chains that only utilize either the top half or the bottom half of the LAB  
before connecting to the next LAB. This leaves the other half of the ALMs  
in the LAB available for implementing narrower fan-in functions in  
normal mode. Carry chains that use the top four ALMs in the first LAB  
carry into the top half of the ALMs in the next LAB within the column.  
Carry chains that use the bottom four ALMs in the first LAB carry into the  
bottom half of the ALMs in the next LAB within the column. Every other  
column of LABs is top-half bypassable, while the other LAB columns are  
bottom-half bypassable.  
See the “MultiTrack Interconnect” on page 2–22 section for more  
information on carry chain interconnect.  
Shared Arithmetic Mode  
In shared arithmetic mode, the ALM can implement a three-input add. In  
this mode, the ALM is configured with four 4-input LUTs. Each LUT  
either computes the sum of three inputs or the carry of three inputs. The  
output of the carry computation is fed to the next adder (either to adder1  
in the same ALM or to adder0of the next ALM in the LAB) via a  
dedicated connection called the shared arithmetic chain. This shared  
arithmetic chain can significantly improve the performance of an adder  
tree by reducing the number of summation stages required to implement  
an adder tree. Figure 2–13 shows the ALM in shared arithmetic mode.  
Altera Corporation  
May 2007  
2–17  
Stratix II Device Handbook, Volume 1  
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