Timing Model
Table 5–70. Stratix II IOE Programmable Delay on Row Pins
Note (1)
Minimum
Timing (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Available
Settings
Parameter
Paths Affected
Min
Max
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
Input delay from Pad to I/O
8
64
2
0
0
1,697
1,782
0
0
2,876
3,020
0
3,308
0
3,853
pin to internal
cells
dataout to logic
array
Input delay from Pad to I/O input
0
0
1,956
2,054
0
0
3,270
3,434
0
0
0
3,761
575
0
0
0
4,381
670
pin to input
register
register
Delay from
I/O output
0
0
316
332
0
0
525
525
output register
to output pin
register to pad
Output enable
pin delay
tXZ, tZX
2
0
0
305
320
0
0
507
507
556
647
Notes to Table 5–70:
(1) The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
(2) The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
(3) The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Default Capacitive Loading of Different I/O Standards
See Table 5–71 for default capacitive loading of different I/O standards.
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 1
of 2)
I/O Standard
CapacitiveLoad Unit
LVTTL
LVCMOS
2.5 V
0
0
pF
pF
pF
pF
pF
pF
pF
pF
0
1.8 V
0
1.5 V
0
PCI
10
10
0
PCI-X
SSTL-2 Class I
5–52
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
