High-Speed Differential I/O with DPA Support
Dedicated Circuitry with DPA Support
Stratix II devices support source-synchronous interfacing with LVDS or
HyperTransport signaling at up to 1 Gbps. Stratix II devices can transmit
or receive serial channels along with a low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1
through 32. For example, a HyperTransport technology application
where the data rate is 1,000 Mbps and the clock rate is 500 MHz would
require that W be set to 2. The SERDES factor J determines the parallel
data width to deserialize from receivers or to serialize for transmitters.
The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to
equal the PLL clock-multiplication W value. A design using the dynamic
phase aligner also supports all of these J factor values. For a J factor of 1,
the Stratix II device bypasses the SERDES block. For a J factor of 2, the
Stratix II device bypasses the SERDES block, and the DDR input and
output registers are used in the IOE. Figure 2–58 shows the block diagram
of the Stratix II transmitter channel.
Figure 2–58. Stratix II Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
+
–
Up to 1 Gbps
10
10
Dedicated
Transmitter
Interface
Local
Interconnect
diffioclk
load_en
refclk
Fast
PLL
Regional or
global clock
Each Stratix II receiver channel features a DPA block for phase detection
and selection, a SERDES, a synchronizer, and a data realigner circuit. You
can bypass the dynamic phase aligner without affecting the basic source-
synchronous operation of the channel. In addition, you can dynamically
switch between using the DPA block or bypassing the block via a control
signal from the logic array. Figure 2–59 shows the block diagram of the
Stratix II receiver channel.
2–100
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
