欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP2C8T144I8N的Datasheet PDF文件第368页浏览型号EP2C8T144I8N的Datasheet PDF文件第369页浏览型号EP2C8T144I8N的Datasheet PDF文件第370页浏览型号EP2C8T144I8N的Datasheet PDF文件第371页浏览型号EP2C8T144I8N的Datasheet PDF文件第373页浏览型号EP2C8T144I8N的Datasheet PDF文件第374页浏览型号EP2C8T144I8N的Datasheet PDF文件第375页浏览型号EP2C8T144I8N的Datasheet PDF文件第376页  
Active Serial Configuration (Serial Configuration Devices)  
You should put a buffer before the DATAand DCLKoutput from the  
master Cyclone II device to avoid signal strength and signal integrity  
issues. The buffer should not significantly change the DATA-to-DCLK  
relationships or delay them with respect to other AS signals (ASDIand  
nCS). Also, the buffer should only drive the slave Cyclone II devices, so  
that the timing between the master Cyclone II device and serial  
configuration device is unaffected.  
This configuration method supports both compressed and uncompressed  
SOFs. Therefore, if the configuration bitstream size exceeds the capacity  
of a serial configuration device, you can enable the compression feature  
in the SOF file used or you can select a larger serial configuration device.  
Estimating AS Configuration Time  
The AS configuration time is the time it takes to transfer data from the  
serial configuration device to the Cyclone II device. The Cyclone II DCLK  
output (generated from an internal oscillator) clocks this serial interface.  
As listed in Table 13–5, if you are using the 40-MHz oscillator, the DCLK  
minimum frequency is 20 MHz (50 ns). Therefore, the maximum  
configuration time estimate for an EP2C5 device (1,223,980 bits of  
uncompressed data) is:  
RBF size × (maximum DCLKperiod / 1 bit per DCLKcycle) =  
estimated maximum configuration time  
1,223,980 bits × (50 ns / 1 bit) = 61.2 ms  
To estimate the typical configuration time, use the typical DCLKperiod  
listed in Table 13–5. With a typical DCLKperiod of 38.46 ns, the typical  
configuration time is 47.1 ms. Enabling compression reduces the amount  
of configuration data that is transmitted to the Cyclone II device, which  
also reduces configuration time. On average, compression reduces  
configuration time by 50%.  
13–18  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007  
 复制成功!